Semiconductor device guaranteeing stable operation

ABSTRACT

A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first variable current to the first sensing amplifier; and a second variable current source supplying or flowing out a second variable current to the second sensing amplifier. A current amount of the first variable current is different from a current amount of the second variable current.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2008-0039347, filed on 28 Apr. 2008, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND

In conventional semiconductor devices, a half VDD precharging method isused to precharge a bitline pair. The half VDD precharging methoddenotes a method of precharging a bit line and a complementary bitlinewith a half level of a VDD voltage.

SUMMARY

Exemplary embodiments of the present invention provide a semiconductordevice capable of guaranteeing a stable operation.

According to an exemplary embodiment of the present invention, there isprovided a semiconductor device comprising: a data line pair consistingof a data line and a complementary data line; a first sensingamplification unit consisting of a first sensing amplifier and a secondsensing amplifier that are cross-coupled with the data line and thecomplementary data line; a first variable current sourcesupplying/extracting a first variable current to/from the first sensingamplifier; and a second variable current source supplying/extracting asecond variable current to/from the second sensing amplifier, wherein acurrent amount of the first variable current is different from a currentamount of the second variable current.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be understood inmore detail from the following descriptions taken in conjunction withthe attached drawings, in which:

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present invention;

FIG. 2 is a block diagram illustrating detailed structures of a firstvariable current source and a second variable current source of thesemiconductor device illustrated in FIG. 1;

FIG. 3 is a circuit diagram of the semiconductor device illustrated inFIG. 1, according to an exemplary embodiment of the present invention;

FIG. 4 is a timing diagram for describing a case where a first memorycell illustrated in FIG. 3 is selected;

FIG. 5 is a timing diagram for describing a case where a second memorycell illustrated in FIG. 3 is selected;

FIG. 6 is a circuit diagram of the semiconductor device illustrated inFIG. 1, according to an exemplary embodiment of the present invention;

FIG. 7 is a timing diagram for describing a case where a first memorycell illustrated in FIG. 6 is selected;

FIG. 8 is a timing diagram for describing a case where a second memorycell illustrated in FIG. 6 is selected;

FIG. 9 is a block diagram of a semiconductor device according to anexemplary embodiment of the present invention;

FIG. 10 is a circuit diagram of the semiconductor device illustrated inFIG. 9, according to an exemplary embodiment of the present invention;

FIG. 11 is a timing diagram for describing an operation of thesemiconductor device illustrated in FIG. 10;

FIG. 12 is a circuit diagram of the semiconductor device illustrated inFIG. 9, according to an exemplary embodiment of the present invention;

FIG. 13 is a circuit diagram of a semiconductor device according to anexemplary embodiment of the present invention;

FIG. 14 is a circuit diagram of a semiconductor device according to anexemplary embodiment of the present invention;

FIG. 15 is a circuit diagram of a semiconductor device according to anexemplary embodiment of the present invention; and

FIG. 16 is a timing diagram for describing an operation of thesemiconductor device illustrated in FIG. 15.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The attached drawings for illustrating exemplary embodiments of thepresent invention are referred to in order to gain a sufficientunderstanding of the present invention, the merits thereof, and theobjectives accomplished by the implementation of the present invention.

Hereinafter, the present invention will be described in detail byexplaining exemplary embodiments of the invention with reference to theattached drawings. Like reference numerals in the drawings denote likeelements.

FIG. 1 is a block diagram of a semiconductor device according to anexemplary embodiment of the present invention. Referring to FIG. 1, thesemiconductor device includes a data line pair 141, a sensingamplification unit 110, a first variable current source 130, and asecond variable current source 140.

The data line pair 141 may include a data line 142 and a complementarydata line 144. For example, the data line pair 141 including the dataline 142 and the complementary data line 144 may be a bit line pairincluding a bit line and a complementary bit line. The bit line pair isonly an example, and exemplary embodiments of the present invention maybe applied to data line pairs other than the bit line pair including abit line and a complementary bit line.

The sensing amplification unit 110 includes a first sensing amplifier112 and a second sensing amplifier 114. The first sensing amplifier 112and the second sensing amplifier 114 are cross-coupled with the dataline 142 and the complementary data line 144, respectively. The firstvariable current source 130 supplies or extracts a first variablecurrent I1 to or from the first sensing amplifier 112, and the secondvariable current source 140 supplies or extracts a second variablecurrent I2 to or from the second sensing amplifier 114.

The first sensing amplifier 112 and the second sensing amplifier 114sense the voltage level of the data line pair 141, and amplify thevoltage level of the data line pair 141 by supplying or extracting apredetermined current to or from the data line pair 141. The amount ofcurrent supplied/extracted by the first sensing amplifier 112 to/fromthe data line 142 may vary according to the voltage level of thecomplementary data line 144. The amount of current supplied/extracted bythe second sensing amplifier 114 to/from the complementary data line 144may vary according to the voltage level of the data line 142. Forexample, when the voltage level of the data line 142 is increased, theamount of current supplied/extracted by the second sensing amplifier 114may be decreased. Alternatively, when the voltage level of the data line142 is increased, the amount of current supplied/extracted by the secondsensing amplifier 114 may be increased. Also, when the voltage level ofthe data line 142 is equal to the voltage level of the complementarydata line 144 and the first variable current I1 is greater than thesecond variable current I2, the first sensing amplifier 112 that hasreceived the first variable current I1 may supply/extract a currentto/from the data line 142, and the second sensing amplifier 114 that hasreceived the second variable current I2, which is less than the firstvariable current I1, may not supply/extract a current to/from thecomplementary data line 144.

If it is assumed that the amount of the first variable current I1supplied/extracted to/from the first sensing amplifier 112 is identicalwith that of the second variable current I2 supplied/extracted to/fromthe second sensing amplifier 114, when the voltage levels of the dataline 142 and the complementary data line 144 are different from eachother, the amounts of current supplied/extracted by the first and secondsensing amplifiers 112 and 114 to the data line 142 and thecomplementary data line 144, respectively, differ. Thus, the first andsecond sensing amplifiers 112 and 114 can properly perform sensingamplification operations. On the other hand, when the voltage levels ofthe data line 142 and the complementary data line 144 are identical witheach other, the amounts of current supplied/extracted by the first andsecond sensing amplifiers 112 and 114 to/from the data line 142 and thecomplementary data line 144, respectively, are the same as each other.Thus, it is difficult for the first and second sensing amplifiers 112and 114 to properly perform sensing amplification operations.

In the semiconductor device according to the current exemplaryembodiment, however, the amount of the first variable current I1supplied/extracted by the first variable current source 130 to/from thefirst sensing amplifier 112 is different from that of the secondvariable current I2 supplied/extracted by the second variable currentsource 140 to/from the second sensing amplifier 114. Because the firstsensing amplifier 112 and the second sensing amplifier 114 receivedifferent amounts of current, even when the voltage levels of the dataline 142 and the complementary data line 144 are identical with eachother, the amounts of current supplied/extracted by the first sensingamplifier 112 and the second sensing amplifier 114 to/from the data line142 and the complementary data line 144 are set to be different fromeach other. Accordingly, in both the case where the voltage levels ofthe data line 142 and the complementary data line 144 are identical witheach other and the case where the voltage levels of the data line 142and the complementary data line 144 are different from each other, thefirst and second sensing amplifiers 112 and 114 can properly performsensing amplification operations.

The first sensing amplifier 112 and the second sensing amplifier 114included in the semiconductor device according to the current exemplaryembodiment may be designed so as to supply/extract identical amounts ofcurrent under the same condition. In other words, the first sensingamplifier 112 and the second sensing amplifier 114 may be designed so asto have an identical driving ability. Because the semiconductor deviceaccording to the current exemplary embodiment supplies/extractsdifferent amounts of current to/from the first sensing amplifier 112 andthe second sensing amplifier 114, although the first sensing amplifier112 and the second sensing amplifier 114 are designed so as to haveidentical driving abilities, the first sensing amplifier 112 and thesecond sensing amplifier 114 supply/extract different amounts of currentto/from the data line 142 and the complementary data line 144,respectively.

Assuming the first and second sensing amplifiers 112 and 114 aredesigned to have different driving abilities and identical amounts ofcurrent are supplied/extracted to/from the first and second sensingamplifiers 112 and 114, the first and second sensing amplifiers 112 and114 may supply/extract identical amounts of current to/from the dataline pair 141. It is difficult to design the first and second sensingamplifiers 112 and 114, however, so as to have different drivingabilities over a single layout. In the semiconductor device according tothe current exemplary embodiment, however, because different amounts ofcurrent are supplied/extracted to/from the first and second sensingamplifiers 112 and 114, the first and second sensing amplifiers 112 and114 can be designed identically over a single layout, and thusdifficulties in the designing process do not occur.

In exemplary embodiments of the present invention, the first and secondsensing amplifiers 112 and 114 may be designed so as to have differentdriving abilities, and different amounts of current may besupplied/extracted to/from the first and second sensing amplifiers 112and 114. In this case, in order to supply/extract different amounts ofcurrent to/from the data line pair 141, either adjustment of adifference between the driving abilities and the first and secondsensing amplifiers 112 and 114 or adjustment of the amounts of currentsupplied/extracted to/from the first and second sensing amplifiers 112and 114 may be employed.

According to which of a first memory cell 172 connected to the data line142 and a second memory cell 174 connected to the complementary dataline 144 is selected, the current amounts of the first and secondvariable currents I1 and I2 can be changed. When the first memory cell172 connected to the data line 142 is selected, the second variablecurrent I2 may be adjusted to be greater than the first variable currentI1. On the other hand, when the second memory cell 174 connected to thecomplementary data line 144 is selected, the second variable current I2may be adjusted to be less than the first variable current I1. In otherwords, when the first memory cell 172 is selected, a greater amount ofcurrent is supplied/extracted to/from the second sensing amplifier 114than to the first sensing amplifier 112. When the second memory cell 174is selected, a greater amount of current is supplied/extracted to/fromthe first sensing amplifier 112 than to the second sensing amplifier114. As described above, because a greater amount of current is suppliedto one of the first and second sensing amplifiers 112 and 114, even whenthe voltage levels of the data line 142 and the complementary data line144 are identical with each other, one of the voltage levels of the dataline 142 and the complementary data line 144 can be changed.

Before the data line pair 141 is sensed and amplified, the data linepair 141 may be precharged with a predetermined voltage level. Forexample, the data line pair 141 may be precharged with a ground voltageor a power supply voltage. When the data line pair 141 is prechargedwith the ground voltage, the first and second variable current sources130 and 140 supply the first and second variable currents I1 and I2 tothe first and second sensing amplifiers 112 and 114, respectively. Thefirst and second sensing amplifiers 112 and 114 supply predeterminedcurrents to the data line pair 141 so as to increase the voltage levelof the data line pair 141. On the other hand, when the data line pair141 is precharged with the power supply voltage, the first and secondvariable current sources 130 and 140 extract the first and secondvariable currents I1 and I2 from the first and second sensing amplifiers112 and 114, respectively. The first and second sensing amplifiers 112and 114 extract predetermined amounts of current from the data line pair141 so as to lower the voltage level of the data line pair 141.

When the data line pair 141 is precharged with the ground voltage andthe first memory cell 172 having data ‘0’ is selected, the voltage levelof the data line 142 connected to the first memory cell 172 is identicalwith the voltage level of the complementary data line 144. Because thedata line pair 141 has been precharged with the ground voltage, thefirst and second variable current sources 130 and 140 supply the firstand second variable currents I1 and I2, respectively. In addition,because the first memory cell 172 is selected, the second variablecurrent I2 supplied to the second sensing amplifier 114 is greater thanthe first variable current I1 supplied to the first sensing amplifier112. Accordingly, the voltage level of the complementary data line 144increases.

On the other hand, when the data line pair 141 is precharged with theground voltage and the first memory cell 172 having data ‘1’ isselected, the voltage level of the data line 142 is greater than thevoltage level of the complementary data line 144. Because the data linepair 141 has been precharged with the ground voltage, the first andsecond variable current sources 130 and 140 supply the first and secondvariable currents I1 and I2. In addition, because the voltage level ofthe data line 142 is high, the amount of current supplied to the firstsensing amplifier 112 increases, and thus the voltage level of the dataline 142 increases.

A sensing amplification operation of the data line pair 141 performedafter the data line pair 141 has been precharged with the power supplyvoltage corresponds to a precharge of the data line pair 141 with theground voltage, except that the first and second variable currents I1and I2 are caused to flow out of the first and second sensing amplifiers112 and 114. Thus, a detailed description of the sensing amplificationoperation of the data line pair 141 will be omitted.

FIG. 2 is a block diagram illustrating detailed structures of the firstvariable current source 130 and the second variable current source 140illustrated in FIG. 1. Referring to FIG. 2, the first and secondvariable current sources 130 and 140 may include a first sub currentsource 132 and a second sub current source 134 and a third sub currentsource 146 and a fourth sub current source 148, respectively. The firstsub current source 132 and the second sub current source 134 included inthe first variable current source 130 are connected to each other inparallel, and the third sub current source 146 and the fourth subcurrent source 148 included in the second variable current source 140are connected to each other in parallel.

The first sub current source 132 and the third sub current source 146are always activated, while the second sub current source 134 and thefourth sub current source 148 are each selectively activated.Accordingly, the current amount of the first variable current I1supplied by the first variable current source 130 and the current amountof the second variable current I2 supplied/flowed out by the secondvariable current source 140 can be changed. For example, when the firstmemory cell 172 connected to the data line 142 is selected, the secondsub current source 134 may be inactivated and the fourth sub currentsource 148 may be activated. In this case, the current amount of thesecond variable current I2 is greater than the current amount of thefirst variable current I1. On the other hand, when the second memorycell 174 connected to the complementary data line 144 is selected, thesecond sub current source 134 may be activated and the fourth subcurrent source 148 may be inactivated. In this case, the current amountof the first variable current I1 is greater than the current amount ofthe second variable current I2.

The first through fourth sub current sources 132, 134, 146, and 148 maybe manufactured so as to supply or flow out identical amounts ofcurrent.

FIG. 3 is a circuit diagram of the semiconductor device illustrated inFIG. 1, according to an exemplary embodiment of the present invention.The semiconductor device illustrated in FIG. 3 is constructed so as tobe precharged with a ground voltage.

Referring to FIG. 3, the first and second variable current sources 130and 140 increase the voltage level of the data line pair 141 that hasalready been precharged with a ground voltage, by supplying the firstand second variable currents I1 and I2 to the data line pair 141.

The first variable current source 130 may include two PMOS transistors,namely, first and second PMOS transistors P132 and P134, and the secondvariable current source 140 may include two PMOS transistors, namely,third and fourth PMOS transistors P146 and P148. The first throughfourth PMOS transistors P132, P134, P146, and P148 may respectivelyserve as the first through fourth sub current sources 132, 134, 146, and148 shown in FIG. 2. The first and second sensing amplifiers 112 and 114of the sensing amplification unit 110 may include a PMOS transistor as afirst sensing amplification transistor P112 and a PMOS transistor as asecond sensing amplification transistor P114, respectively.

The first PMOS transistor P132 and the third PMOS transistor P146 supplycurrents in response to a first control signal LAPG. The second PMOStransistor P134 supplies a current in response to a second controlsignal LACPG. The fourth PMOS transistor P148 supplies a current inresponse to a third control signal LATPG.

The first through fourth PMOS transistors P132, P134, P146, and P148 maybe designed so as to have identical sizes. In addition, the firstsensing amplification transistor P112 and the second sensingamplification transistor P114 may be designed so as to have identicalsizes. Accordingly, problems can be prevented from occurring during aprocess of manufacturing transistors of different sizes on a singlelayout. On the other hand, the first through fourth PMOS transistorsP132, P134, P146, and P148 could also be designed to have differentsizes. In addition, the first sensing amplification transistor P112 andthe second sensing amplification transistor P114 may be designed to havedifferent sizes.

FIG. 4 is a timing diagram for describing a case where the first memorycell 172 of FIG. 3 is selected.

The case where the first memory cell 172 is selected will now bedescribed with reference to FIGS. 3 and 4. When the logic level of afirst memory cell control signal MLT transitions to logic high, thefirst memory cell 172 is selected. If data stored in the first memorycell 172 is ‘1’, that is, if a first capacitor C172 is charged with anelectric charge, the electric charge of the first capacitor C172 isshared with the data line 142. Accordingly, the voltage level of thedata line 142 is increased to be greater than the voltage level of thecomplementary data line 144, which is the precharged ground voltagelevel. On the other hand, if the data stored in the first memory cell172 is ‘0’, that is, if the first capacitor C172 is not charged with anelectric charge, the voltage level of the data line 142 stays the sameprecharged ground voltage level as that of the complementary data line144.

After the first memory cell 172 is selected due to a transition of thelogic level of the first memory cell control signal WLT to logic high,logic levels of the first control signal LAPG and the third controlsignal LATPG transition to logic low, and the second control signalLACPG maintains logic high. Accordingly, the first PMOS transistor P132,the third PMOS transistor P142, and the fourth PMOS transistor P144 areturned on, and the second PMOS transistor P134 is turned off. In thiscase, the first variable current I1 is a current flowing in the firstPMOS transistor P132, and the second variable current I2 is a sum ofcurrent flowing in the third PMOS transistor P142 and current flowing inthe fourth PMOS transistor P144. In other words, the second variablecurrent I2 is greater than the first variable current I1.

When the voltage level of the data line 142 is increased to be higherthan that of the complementary data Line 144 due to the storage of data‘1’ in the first memory cell 172 and charge is shared between the dataline 142 and the first memory cell 172, the level of a voltage appliedto a gate of the second sensing amplification transistor P114 isincreased to be higher than that of a voltage applied to a gate of thefirst sensing amplification transistor P112. Accordingly, the drivingability of the first sensing amplification transistor P112 is increasedto be higher than that of the second sensing amplification transistorP114, and the first sensing amplification transistor P112 supplies thefirst variable current I1 received from the first variable currentsource 130 to the data line 142 in order to increase the voltage levelof the data line 142. Thus, a difference between the voltage levels ofthe data line 142 and the complementary data line 144 increases.

When the voltage levels of the data line 142 and the complementary dataline 144 are identical with each other due to the storage of data ‘0’ inthe first memory cell 172, the level of a voltage applied to the gate ofthe second sensing amplification transistor P114 becomes the same asthat of a voltage applied to the gate of the first sensing amplificationtransistor P112. Because the second variable current I2 is greater thanthe first variable current I1 when the first memory cell 172 isselected, however, the driving ability of the second sensingamplification transistor P114 is increased to be higher than that of thefirst sensing amplification transistor P112. Accordingly, the secondsensing amplification transistor P114 supplies the second variablecurrent I2 received from the second variable current source 140 to thecomplementary data line 144, thereby increasing the voltage level of thecomplementary data line 144. The voltage level of the data line 142 iskept at the precharged ground voltage level, and thus the differencebetween the voltage levels of the data line 142 and the complementarydata line 144 increases.

FIG. 5 is a timing diagram for describing a case where the second memorycell 174 of FIG. 3 is selected.

The case where the second memory cell 174 of FIG. 3 is selected will nowbe described with reference to FIGS. 3 and 5. When the logic level of asecond memory cell control signal WLC transitions to logic high, thesecond memory cell 174 is selected. If data stored in the second memorycell 174 is ‘1’, that is, if a second capacitor C174 is charged with anelectric charge, the electric charge of the second capacitor C174 isshared with the complementary data line 144. Accordingly, the voltagelevel of the complementary data line 144 is increased to be greater thanthat of the data line 142. On the other hand, if the data stored in thesecond memory cell 174 is ‘0’, that is, if the second capacitor C174 isnot charged with an electric charge, the voltage level of thecomplementary data line 144 stays the same as that of the data line 142.

After the second memory cell 174 is selected due to a transition of thelogic level of the second memory cell control signal WLC to logic high,logic levels of the first control signal LAPG and the second controlsignal LACPG transition to logic low, and the third control signal LATPGmaintains logic high. Accordingly, the first PMOS transistor P132, thesecond PMOS transistor P134, and the third PMOS transistor P146 areturned on, and the fourth PMOS transistor P148 is turned off. In thiscase, the first variable current I1 is a sum of current flowing in thefirst PMOS transistor P132 and current flowing in the second PMOStransistor P134 and the second variable current I2 is a current flowingin the third PMOS transistor P146. In other words, the second variablecurrent I2 is less than the first variable current I1.

When the voltage level of the complementary data line 144 is increasedto be higher than that of the data line 142 due to the storage of data‘1’ in the second memory cell 174 and the sharing of charge between thecomplementary data line 144 and the second memory cell 174, the level ofa voltage applied to the gate of the first sensing amplificationtransistor P112 is increased to be higher than that of a voltage appliedto the gate of the second sensing amplification transistor P114.Accordingly, the driving ability of the second sensing amplificationtransistor P114 is increased to be higher than that of the first sensingamplification transistor P112, and the second sensing amplificationtransistor P114 supplies the second variable current I2 received fromthe second variable current source 140 to the complementary data line144 in order to increase the voltage level of the complementary dataline 144. The voltage level of the data line 142 is kept at a groundvoltage level, and thus the difference between the voltage levels of thedata line 142 and the complementary data line 144 increases.

When the voltage levels of the complementary data line 144 and the dataline 142 are identical with each other due to the storage of data ‘0’ inthe second memory cell 174, the level of a voltage applied to the gateof the first sensing amplification transistor P112 becomes the same asthat of a voltage applied to the gate of the second sensingamplification transistor P114. Because the first variable current I1 isgreater than the second variable current I2 when the second memory cell174 is selected, however, the driving ability of the first sensingamplification transistor P112 is increased to be higher than that of thesecond sensing amplification transistor P114. Accordingly, the firstsensing amplification transistor P112 supplies the first variablecurrent I1 received from the first variable current source 130 to thedata line 142, thereby increasing the voltage level of the data line142. The voltage level of the complementary data line 144 is kept at aground voltage level, and thus the difference between the voltage levelsof the data line 142 and the complementary data line 144 increases.

FIG. 6 is a circuit diagram of the semiconductor device illustrated inFIG. 1, according to an exemplary embodiment of the present invention.The semiconductor device illustrated in FIG. 6 is constructed so as tobe precharged with a power supply voltage.

Referring to FIG. 6, the first and second variable current sources 130and 140 decrease the voltage level of the data line pair 141 that hasalready been precharged with a power supply voltage, by flowing out thefirst and second variable currents I1 and I2 to the data line pair 141.

The first variable current source 130 may include two NMOS transistors,namely, first and second NMOS transistors N132 and N134, and the secondvariable current source 140 may include two NMOS transistors, namely,third and fourth NMOS transistors N146 and N148. The first throughfourth NMOS transistors N132, N134, N146, and N148 may respectivelyserve as the first through fourth sub current sources 132, 134, 146, and148. The first and second sensing amplifiers 112 and 114 may include anNMOS transistor N112 and an NMOS transistor N114, respectively.

The first NMOS transistor N132 and the third NMOS transistor N146 flowout currents in response to a first control signal LANG. The second NMOStransistor N134 flows out a current in response to a second controlsignal LACNG. The fourth NMOS transistor N148 flows out a current inresponse to a third control signal LATNG.

FIG. 7 is a timing diagram for describing a case where the first memorycell 172 of FIG. 6 is selected.

The case where the first memory cell 172 is selected will now bedescribed with reference to FIGS. 6 and 7. When the logic level of afirst memory cell control signal WLT transitions to logic high, thefirst memory cell 172 is selected. If data stored in the first memorycell 172 is ‘0’, an electric charge is shared between the firstcapacitor C172 and the data line 142. Accordingly, the voltage level ofthe data line 142 is decreased from the power supply voltage level to beless than that of the complementary data line 144. On the other hand, ifthe data stored in the first memory cell 172 is ‘1’, the voltage levelof the data line 142 stays the same state as that of the complementarydata line 144, which is the precharged power supply voltage level.

After the first memory cell 172 is selected due to a transition of thelogic level of the first memory cell control signal WLT to logic high,logic levels of the first control signal LANG and the third controlsignal LATNG transition to logic low, and the second control signalLACNG maintains logic high. Accordingly, the first NMOS transistor N132,the third NMOS transistor N142, and the fourth NMOS transistor N148 areturned on, and the second NMOS transistor N134 is turned off. In thiscase, the first variable current I1 is a current flowing in the firstNMOS transistor N132, and the second variable current I2 is a sum of thecurrent flowing in the third NMOS transistor N146 and the currentflowing in the fourth NMOS transistor N148. In other words, the secondvariable current I2 is greater than the first variable current I1.

When the voltage level of the data line 142 is decreased to be less thanthat of the complementary data line 144 due to the storage of data ‘0’in the first memory cell 172 and the sharing of charge between the dataline 142 and the first capacitor C172, the level of a voltage applied toa gate of the second sensing amplification transistor N114 is decreasedto be less than that of a voltage applied to a gate of the first sensingamplification transistor N112. Accordingly, the driving ability of thefirst sensing amplification transistor N112 is increased to be higherthan that of the second sensing amplification transistor N114, and thefirst sensing amplification transistor N112 flows out the first variablecurrent I1 to the first NMOS transistor N132 in order to decrease thevoltage level of the data line 142. The voltage level of thecomplementary data line 144 is kept in the precharged power supplyvoltage level, and thus a difference between the voltage levels of thedata line 142 and the complementary data line 144 increases.

When the voltage levels of the data line 142 and the complementary dataline 144 are identical with each other at the power supply voltage level(the precharged voltage level) due to the storage of data ‘1’ in thefirst memory cell 172, the level of a voltage applied to the gate of thesecond sensing amplification transistor N114 becomes the same as that ofa voltage applied to the gate of the first sensing amplificationtransistor N112. Because the second variable current I2 is greater thanthe first variable current I1 when the first memory cell 172 isselected, however, the driving ability of the second sensingamplification transistor N114 is increased to be higher than that of thefirst sensing amplification transistor N112, Accordingly, the secondvariable current I2 flows out of the second sensing amplificationtransistor N114 to the third and fourth NMOS transistors N146 and N148,thereby decreasing the voltage level of the complementary data line 144.The voltage level of the data line 142 is kept at the precharged powersupply voltage level, and thus the difference between the voltage levelsof the data line 142 and the complementary data line 144 increases.

FIG. 8 is a timing diagram for describing a case where the second memorycell 174 of FIG. 6 is selected.

The case where the second memory cell 174 of FIG. 6 is selected will nowbe described with reference to FIGS. 6 and 8. If data stored in thesecond memory cell 174 is ‘0’, an electric charge is shared between thecomplementary data line 144 and the second capacitor C174. Accordingly,the voltage level of the complementary data line 144 is decreased to beless than that of the data line 142. On the other hand, if the datastored in the second memory cell 174 is ‘1’, the voltage level of thecomplementary data line 144 stays the same state as that of the dataline 142.

After the second memory cell 174 is selected due to a transition of thelogic level of the second memory cell control signal WLC to logic high,logic levels of the first control signal LANG and the second controlsignal LACNG transition to logic high, and the third control signalLATNG maintains logic low. Accordingly, the first NMOS transistor N132,the second NMOS transistor N134, and the third NMOS transistor N146 areturned on, and the fourth NMOS transistor N148 is turned off. In thiscase, the first variable current I1 is a sum of current flowing in thefirst NMOS transistor N132 and current flowing in the second NMOStransistor N134 and the second variable current I2 is a current flowingin the third NMOS transistor N146. In other words, the second variablecurrent I2 is less than the first variable current I1.

When the voltage level of the complementary data line 144 is decreasedto be less than that of the data line 142 due to the storage of data ‘0’in the second memory cell 174 and the sharing of charge between thecomplementary data line 144 and the second capacitor C174, the level ofa voltage applied to the gate of the first sensing amplificationtransistor N112 is decreased to be less than that of a voltage appliedto the gate of the second sensing amplification transistor N114.Accordingly, the driving ability of the second sensing amplificationtransistor N114 is increased to be higher than that of the first sensingamplification transistor N112, and the second variable current I2 flowsout of the second sensing amplification transistor N114 to the thirdNMOS transistor N146 in order to decrease the voltage level of thecomplementary data line 144. The voltage level of the data line 142 iskept in a power supply voltage level, and thus the difference betweenthe voltage levels of the data line 142 and the complementary data line144 increases.

When the voltage levels of the complementary data line 144 and the dataline 142 are identical with each other at a power supply voltage level,that is, the a precharged voltage level, due to the storage of data ‘1’in the second memory cell 174, the level of a voltage applied to thegate of the second sensing amplification transistor N114 becomes thesame as that of a voltage applied to the gate of the first sensingamplification transistor N112. Because the first variable current I1 isgreater than the second variable current I2 when the second memory cell174 is selected, however, the driving ability of the first sensingamplification transistor N112 is increased to be higher than that of thesecond sensing amplification transistor N114. Accordingly, the firstvariable current I1 flows out of the first sensing amplificationtransistor N112 to the first and second NMOS transistors N132 and N134,thereby decreasing the voltage level of the data line 142. The voltagelevel of the complementary data line 144 is kept at a power supplyvoltage level, and thus the difference between the voltage levels of thedata line 142 and the complementary data line 144 increases.

Although the first variable current source 130 and the second variablecurrent source 140 of FIG. 3 include PMOS transistors, the PMOStransistors may be replaced with NMOS transistors. All of the PMOStransistors may be replaced by NMOS transistors, however, or only someof the PMOS transistors may be replaced by NMOS transistors. Althoughthe first sensing amplifier 112 and the second sensing amplifier 114 ofFIG. 3 include PMOS transistors, the present invention is not limitedthereto and, thus, the PMOS transistors may be replaced with NMOStransistors.

Although the first variable current source 130, the second variablecurrent source 140, the first sensing amplifier 112, and the secondsensing amplifier 114 of FIG. 6 include NMOS transistors, some of theNMOS transistors may be replaced with PMOS transistors.

FIG. 9 is a block diagram of a semiconductor device according to anembodiment of the present invention. In contrast with the semiconductordevice of FIG. 1, the semiconductor device of FIG. 9 may further includea precharging unit 990 to precharge a data line pair 941 with a powersupply voltage or a ground voltage.

In contrast with the semiconductor device of FIG. 1, the semiconductordevice of FIG. 9 may her include a second sensing amplification unit980. The second sensing amplification unit 980 may include a thirdsensing amplifier 982 and a fourth sensing amplifier 984. The thirdsensing amplifier 982 and the fourth sensing amplifier 984 may becross-coupled with a data line 942 and a complementary data line 944.

The third sensing amplifier 982 and the fourth sensing amplifier 984 areactivated a predetermined period of time after a first sensingamplification unit 910 is activated, thereby removing an influence of asensing amplifier having a low driving ability from among the firstsensing amplifier 912 and the second sensing amplifier 914. For example,if the first variable current I1 is greater than the second variablecurrent I2, a driving ability of the first sensing amplifier 912 isgreater than that of the second sensing amplifier 914. In this case, thevoltage level of the data line 942 is changed by the first sensingamplifier 912, as already described above. A second sensing amplifier914, however, also slightly changes the voltage level of thecomplementary data line 944. As then seen, a variation of the voltagelevel of the complementary data line 944 is less than that of thevoltage level of the data line 942. In addition, the first sensingamplifier 912 and the second sensing amplifier 914 increase or decreasethe voltage level of the data line pair 941. When the voltage level ofthe complementary data line 944 is changed by a second sensing amplifier914, a difference between the voltage levels of the data line 942 andthe complementary data line 944 decreases. In order to solve the problemof the decrease in the voltage level difference, the third sensingamplifier 982 and the fourth sensing amplifier 984 decrease (orincrease) the voltage level of the complementary data line 944, which isincreased (or decreased) by the second sensing amplifier 914, after thelogic level of a fourth control signal LAB is changed.

FIG. 10 is a circuit diagram of the semiconductor device illustrated inFIG. 9, according to an exemplary embodiment of the present invention.

Referring to FIG. 10, the precharging unit 990 includes a firstprecharging NMOS transistor N992 and a second precharging NMOStransistor N994. A ground voltage is applied to a common terminal of thefirst precharging NMOS transistor N992 and the second precharging NMOStransistor N994. The first precharging NMOS transistor N992 and thesecond precharging NMOS transistor N994 are turned on in response to aprecharge control signal PRE and precharge the data line pair 941 withthe ground voltage.

The second sensing amplification unit 980 includes a third sensingamplification transistor N982 and a fourth sensing amplificationtransistor N984. The third sensing amplification transistor N982 and thefourth sensing amplification transistor N984 are cross-coupled with thedata line 942 and the complementary data line 944. The remainingelements shown in FIG. 10 but not described, correspond to identicalelements already described in regard to the above exemplary embodimentsand have corresponding reference numerals.

FIG. 11 is a timing diagram for describing an operation of thesemiconductor device illustrated in FIG. 10.

Referring to FIG. 11, the logic level of the fourth control signal LABtransitions to logic low after the lapse of a predetermined period oftime from a point in time when a first control signal LAPG and a thirdcontrol signal LATPG transition to logic low.

FIG. 11 illustrates an operation of the semiconductor device of FIG. 10when the first memory cell 972 is selected.

When data stored in the first memory cell 972 is ‘1’, if a first memorycell control signal WLT transitions to logic high within a period A-B,the first memory cell 972 is selected and an electrical charge of afirst capacitor C972 is shared with the data line 942. As a result, thevoltage level of the data line 942 slightly increases. Meanwhile, thevoltage level of the complementary data line 944 is kept at a groundvoltage level, that is, the precharged voltage level. Then, if the firstcontrol signal LAPG and the third control signal LATPG transition tologic low within a period B-C, a first sensing amplification transistorP912 and a second sensing amplification transistor P914 respectivelysupply currents to the data line 942 and the complementary data line944, thereby increasing the voltage levels of the data line 942 and thecomplementary data line 944. Because the voltage level of the data line942 is higher than the voltage level of the complementary data line 944within the period B-C, the level of a voltage applied to a gate of thesecond sensing amplification transistor P914 is higher than that of avoltage applied to a gate of the first sensing amplification transistorP912. Therefore, an amount by which the voltage level of thecomplementary data line 944 is increased by the second sensingamplification transistor P914 is less an that by which the voltage levelof the data line 942 is increased by the first sensing amplificationtransistor P912.

Then, the logic level of the fourth control signal LAB transitions tologic low within a period C-D. Within the period C-D, the third sensingamplification transistor N982 and the fourth sensing amplificationtransistor N984 allow currents to flow out of the data line 942 and thecomplementary data line 944. Because the voltage level of the data line942 is higher than the voltage level of the complementary data line 944within the period C-D, the level of a voltage applied to a gate of thefourth sensing amplification transistor N984 is higher than that of avoltage applied to a gate of the third sensing amplification transistorN982. Therefore, the fourth sensing amplification transistor N984 has astrong driving ability, the voltage level of the data line 942 seldomdecreases, and the voltage level of the complementary data line 944decreases. Thus, the voltage level of the complementary data line 944,which is increased by the first sensing amplification transistor P912 inthe period B-C, can be decreased within the period C-D.

When data stored in the first memory cell 972 is ‘0’, the voltage levelsof the data line 942 and the complementary data line 944 are keptidentical to each other within the period A-B. Then, the logic levels ofthe first control signal LAPG and the third control signal LATPGtransition to logic low within the period B-C, the first sensingamplification transistor P912 and the second sensing amplificationtransistor P914 respectively supply currents to the data line 942 andthe complementary data line 944, thereby increasing the voltage levelsof the data line 942 and the complementary data line 944. Within theperiod B-C, the voltage level of the data line 942 is equal to that ofthe complementary data line 944, and the second variable current I2supplied to the second sensing amplification transistor P914 is greaterthan the first variable current I1 supplied to the first sensingamplification transistor P912. Therefore, an amount by which the voltagelevel of the complementary data line 944 is increased by the secondsensing amplification transistor P914 is higher than that by which thevoltage level of the data line 942 is increased by the first sensingamplification transistor P912.

Thereafter, the logic level of the fourth control signal LAB transitionsto logic low within the period C-D. Within the period C-D, the thirdsensing amplification transistor N982 and the fourth sensingamplification transistor N984 allow currents to flow out of the dataline 942 and the complementary data line 944, respectively. Because thevoltage level of the complementary data line 944 is higher than thevoltage level of the data line 942 within the period C-D, the level ofthe voltage applied to the gate of the third sensing amplificationtransistor N982 is higher than that of the voltage applied to the gateof the fourth sensing amplification transistor N984. Therefore, thesecond sensing amplification transistor N982 has a strong drivingability, the voltage level of the complementary data line 944 seldomdecreases, and the voltage level of the data line 942 decreases. Thus,the voltage level of the data line 942, which is increased by the FIRSTsensing amplification transistor P912 within the period B-C, may bedecreased within the period C-D.

Up to now, a transition of the fourth control signal LAB from logic highto logic low has been described. The fourth control signal LAB, however,may be maintained at logic-low. In this case, the third sensingamplification transistor N982 and the fourth sensing amplificationtransistor N984 may respectively flow out currents to the data line 942and the complementary data line 944 and, thus, the semiconductor devicemay perform an operation similar to an operation performed when thefourth control signal LAB transitions from logic high to logic low.

Although a case where the second memory cell 974 is selected is notdescribed in connection with FIG. 10, the case where the second memorycell 974 is selected will be understood by one of ordinary skill in theart by referring to what has been described above, and thus a detaileddescription thereof will be omitted.

FIG. 12 is a circuit diagram of the semiconductor device illustrated inFIG. 9, according to an exemplary embodiment of the present invention.

The semiconductor device of FIG. 10 has such a circuit that can beprecharged with a ground voltage, whereas the semiconductor device ofFIG. 12 has such a circuit that can be precharged with a power supplyvoltage. The power supply voltage Vdd is applied to a common terminal ofthe first precharging NMOS transistor N992 and the second prechargingNMOS transistor N994. First and second variable current sources 930 and940 of FIG. 10 supply currents to a data line pair 941, whereas firstand second variable current sources 930 and 940 of FIG. 12 allowcurrents to flow out of the data line pair 941. Except for this, thecomponents of the semiconductor device of FIG. 12 correspond to those ofthe semiconductor device of FIG. 10, respectively, and operations of thecomponents of FIG. 12 correspond to those of the components of FIG. 10,respectively. Therefore, a detailed description of an operation of thesemiconductor device of FIG. 12 will be omitted.

Referring to FIG. 12, a fifth control signal LA fed to the secondsensing amplification unit 980 may be transitioned from logic low tologic high or maintained at logic high.

FIG. 13 is a circuit diagram of a semiconductor device according to anexemplary embodiment of the present invention.

Referring to FIG. 13, the semiconductor device includes a first variablecurrent source 1330, a second variable current source 1340, and aplurality of first sensing amplification units 1300_1, 1300_2, throughto 1300 _(—) n. The remaining elements shown in FIG. 13 but notdescribed, correspond to identical elements already described in regardto the above exemplary embodiments and have corresponding referencenumerals with two digit suffixes preceded by the figure number. Thefirst sensing amplification units 1300_1, 1300_2, through to 1300 _(—) nshare the first variable current source 1330 and the second variablecurrent source 1340, as shown by the encircled connections. In otherwords, the first variable current source 1330 and the second variablecurrent source 1340 supply or flow out currents to the first sensingamplification units 1300_1, 1300_2, through to 1300 _(—) n.

Although the semiconductor device illustrated in FIG. 13 includes thesingle first variable current source 1330 and the single second variablecurrent source 1340, the semiconductor device may also include at leasttwo first variable current sources and at least two second variablecurrent sources. In this case, the first sensing amplification units1300_1, 1300_2, through to 1300 _(—) n may be divided into two or moregroups, and thus each of the groups may share a single first variablecurrent source and a single second variable current source.

FIG. 14 is a circuit diagram of a semiconductor device according to anexemplary embodiment of the present invention. In contrast with thesemiconductor device of FIG. 10, the semiconductor device of FIG. 14further includes a first disconnection unit 1462 and a seconddisconnection unit 1464.

The first disconnection unit 1462 is installed between a first memorycell 1472 and a data line 1442, and connects the first memory cell 1472to, or disconnects the first memory cell 1472 from, the data line 1442.The second disconnection unit 1464 is installed between a second memorycell 1474 and a complementary data line 1444, and connects the secondmemory cell 1474 to or disconnects the second memory cell 1474 from thecomplementary data line 1444. By disconnecting the first and secondmemory cells 1472 and 1474 from a data line pair 1441 by using the firstand second disconnection units 1462 and 1464 as described above, theload applied to the data line pair 1441 can be reduced.

While data stored in the first memory cell 1472 is being transferred tothe data line 1442, the first disconnection unit 1462 connects the firstmemory cell 1472 to the data line 1442. After the transfer of the datastored in the first memory cell 1472 to the data line 1442 is completed,the first memory cell 1472 may be disconnected from the data line 1442.While data stored in the second memory cell 1474 is being transferred tothe complementary data line 1444, the second disconnection unit 1464connects the second memory cell 1474 to the complementary data line1444. After the transfer of the data stored in the second memory cell1474 to the complementary data line 1444 is completed, the second memorycell 1474 may be disconnected from the complementary data line 1444.

Although it is illustrated in FIG. 14 that the first disconnection unit1462 and the second disconnection unit 1464 include a firstdisconnection transistor N1462 and a second disconnection transistorN1464, respectively, this is just an example. In other words, the firstdisconnection transistor N1462 and the second disconnection transistorN1464 may be replaced with other elements that serve as switches. Theremaining elements shown in FIG. 14 but not described, correspond toidentical elements already described in regard to the above exemplaryembodiments and have corresponding reference numerals with two digitsuffixes preceded by the figure number.

Up to now, a case where a first sensing amplifier and a second sensingamplifier are cross-coupled with a data line and a complementary dataline has been described. Exemplary embodiments of the present invention,however, are not limited to the cross-coupling configuration of thefirst and second sensing amplifiers, and the first and second sensingamplifiers may be connected to a data line and a complementary data linein various other ways.

In addition, a case where both first and second variable current sourcessupply variable currents, namely, first and second variable currents,has been described up to now. One of the first variable current sourceand the second variable current source, however, may supply a variablecurrent and the other may supply a constant current. Therefore,different amounts of current may be supplied to the first sensingamplifier and the second sensing amplifier.

FIG. 15 is a circuit diagram of a semiconductor device according to anexemplary embodiment of the present invention. Referring to FIG. 15, thesemiconductor device includes a data line pair 1541, a first sensingamplification unit 1510, a second sensing amplification unit 1580, afirst current source 1530, and a second current source 1540.

The data line pair 1541 includes a data line 1542 and a complementarydata line 1544. The first sensing amplification unit 1510 includes afirst sensing amplifier 1512 and a second sensing amplifier 1514. Thefirst sensing amplifier 1512 and the second sensing amplifier 1514 arecross-coupled with the data line 1542 and the complementary data line1544. The components of the present exemplary embodiment correspond tothe components illustrated in FIG. 3, and thus a detailed descriptionthereof will be omitted. That is, the remaining elements shown in FIG.15 but not described, correspond to identical elements already describedin connection with the above exemplary embodiments and havecorresponding reference numerals with two digit suffixes preceded by thefigure number.

The first current source 1530 supplies a first current to the firstsensing amplifier 1512, and the second current source 1540 supplies asecond current to the second sensing amplifier 1514. In FIG. 3, thefirst and second variable current sources 130 and 140 supply the firstvariable current I1 and the second variable current I2. In FIG. 15,however, the first and second variable current sources 1530 and 1540 maysupply constant currents, namely, the first and second currents. As willbe seen, however, the first and second currents may also be variablecurrents.

The time at which the first current source 1530 supplies the firstcurrent is different from the time at which the second current source1540 supplies the second current. For example, when a first memory cell1572 connected to the data line 1542 is selected, the second current maybe supplied prior to the first current. On the other hand, when a secondmemory cell 1574 connected to the complementary data line 1544 isselected, the first current may be supplied prior to the second current.

FIG. 16 is a timing diagram for describing an operation of thesemiconductor device illustrated in FIG. 15. Referring to FIG. 16, whendata line pair 1541 is charged with a ground voltage and a first memorycell control signal WLT transitions from logic low to logic high, thefirst memory cell 1572 is selected.

If data stored in the first memory cell 1572 is ‘0’, the voltage levelof the data line 1542 is equal to that of the complementary data line1544. Then, when a second control signal LATPG transitions from logichigh to logic low, the second current is supplied to the second sensingamplification transistor P1514 and, thus, the second sensingamplification transistor P1514 increases the voltage level of thecomplementary data line 1544 (see a period B-C). Thereafter, when afirst control signal LACPG transitions from logic high to logic low at apoint in time C, the voltage level of the complementary data line 1544has already been increased to be higher than that of the data line 1542at the point in time C. Thus, the level of a voltage applied to a gateof the first sensing amplification transistor P1512 is higher than thatof a voltage applied to a gate of the second sensing amplificationtransistor P1514, and thus the first sensing amplification transistorP1512 fails to increase the voltage level of the data line 1542.

If data stored in the first memory cell 1572 is ‘1’, the voltage levelof the data line 1542 is increased to be higher than that of thecomplementary data line 1544. Then, when the second control signal LATPGtransitions from logic high to logic low, the second current is suppliedto the second sensing amplification transistor P1514 and, thus, thesecond sensing amplification transistor P1514 slightly increases thevoltage level of the complementary data line 1544 (see a period B-C).Because the voltage level of the data line 1542 is higher than that ofthe complementary data line 1544, the level of the voltage applied tothe gate of the second sensing amplification transistor P1514 is higherthan that of the voltage applied to the gate of the first sensingamplification transistor P1512. Therefore, the first sensingamplification transistor P1512 has a driving ability to supply a higheramount of current than a current supplied to the second sensingamplification transistor P1514. In the period B-C, however, because thefirst current is not supplied to the first sensing amplificationtransistor P1512, the first sensing amplification transistor P1512 failsto increase the voltage level of the data line 1542.

Then, at a point in time C, when the first control signal LACPGtransitions from logic high to logic low, the first sensingamplification transistor P1512 receives the first current and increasesthe voltage level of the data line 1542. After the point in time C, thefirst sensing amplification transistor P1512 operates and, thus, thesecond sensing amplification transistor P1514 no longer increases thevoltage level of the complementary data line 1544.

Although it is illustrated in FIGS. 15 and 16 that the first and secondcurrent sources 1530 and 1540 supply the first and second currents tothe data line pair 1541, the first and second current sources 1530 and1540 may also allow the first and second currents to flow out of thedata line pair 1541. The flow of the first and second currents from thedata line pair 1541 will be understood to one of ordinary skill in theart by referring to FIGS. 15 and 16 and, thus, a detailed descriptionthereof will be omitted.

In a data sensing method according to an exemplary embodiment of thepresent invention, data stored in a data line pair including a data lineand a complementary data line is sensed using a first sensing amplifierand a second sensing amplifier.

The data sensing method according to an exemplary embodiment of thepresent invention includes a precharging operation and a current controloperation. In the precharging operation, the data line pair isprecharged with a first voltage or a second voltage. In the currentcontrol operation, a first variable current is supplied or flowed out tothe first sensing amplifier, and a second variable current is suppliedor flowed out to the second sensing amplifier, such that the currentamount of the first variable current is different from that of thesecond variable current.

In the precharging operation, the data line pair may be precharged witha ground voltage. In this case, in the current control operation, thefirst and second variable currents may be respectively supplied to thefirst and second sensing amplifiers. On the other hand, in theprecharging operation, the data line pair may be precharged with a powersupply voltage. In this case, in the current control operation, thefirst and second variable currents may be flowed out of the first andsecond sensing amplifiers, respectively.

When a first memory cell connected to the data line is selected, thesecond variable current may be increased to be higher than the firstvariable current. On the other hand, when a second memory cell connectedto the complementary data line is selected, the second variable currentmay be decreased to be less than the first variable current.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby one of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention, as defined by the following claims.

1. A semiconductor device comprising: a data line pair comprising a data line and a complementary data line; a first sensing amplification unit comprising a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first variable current to the first sensing amplifier; and a second variable current source supplying or flowing out a second variable current to the second sensing amplifier, wherein a current amount of the first variable current is different from a current amount of the second variable current.
 2. The semiconductor device of claim 1, wherein: when the data line pair is precharged with a ground voltage, the first variable current source and the second variable current source supply the first and second variable currents to the first and second sensing amplifiers, respectively.
 3. The semiconductor device of claim 1 wherein: when the data line pair is precharged with a power supply voltage, the first variable current source and the second variable current source flow out the first and second variable currents to the first and second sensing amplifiers, respectively.
 4. The semiconductor device of claim 1, wherein: when a first memory cell connected to the data line is selected, the second variable current is changed to be greater than the first variable current; and when a second memory cell connected to the complementary data line is selected, the second variable current is changed to be less than the first variable current.
 5. The semiconductor device of claim 1, wherein: the first variable current source comprises a first sub current source and a second sub current source that are connected to each other in parallel; the second variable current source comprises a third sub current source and a fourth sub current source that are connected to each other in parallel; when a first memory cell connected to the data line is selected, the second sub current source is inactivated; and when a second memory cell connected to the complementary data line is selected, the fourth sub current source is inactivated.
 6. The semiconductor device of claim 1, wherein: the first sensing amplifier comprises a first MOS transistor comprising a gate connected to the complementary data line; and the second sensing amplifier comprises a second MOS transistor comprising a gate connected to the data line.
 7. The semiconductor device of claim 6, wherein: a first end of the first MOS transistor is connected to the data line and a second end of the first MOS transistor is connected to the first variable current source; and a first end of the second MOS transistor is connected to the complementary data line and a second end of the second MOS transistor is connected to the second variable current source.
 8. The semiconductor device of claim 1, further comprising: a first memory cell; a second memory cell; a first disconnection unit installed between the first memory cell and the data line, selectively connecting the first memory cell to the data line or disconnecting the first memory cell from the data line; and a second disconnection unit installed between the second memory cell and the complementary data line, selectively connecting the second memory cell to the complementary data line or disconnecting the second memory cell from the complementary data line.
 9. The semiconductor device of claim 8, wherein: while data stored in the first memory cell is being transferred to the data line, the first disconnection unit connects the first memory cell to the data line; and after the transfer of the data stored in the first memory cell to the data line is completed, the first disconnection unit disconnects the first memory cell from the data line; while data stored in the second memory cell is being transferred to the complementary data line, the second disconnection unit connects the second memory cell to the complementary data line; and after the transfer of the data stored in the second memory cell to the complementary data line is completed, the second disconnection unit disconnects the second memory cell from the complementary data line;
 10. The semiconductor device of claim 1, further comprising a precharging unit precharging the data line and the complementary data line with one of a power supply voltage level and a ground voltage level.
 11. The semiconductor device of claim 1, further comprising a second sensing amplification unit comprising a third sensing amplifier and a fourth sensing amplifier that are cross-coupled with the data line and the complementary data line, wherein a control signal is applied to a node between the third sensing amplifier and the fourth sensing amplifier and is enabled after the lapse of a predetermined period of time from a point in time when the first and second variable current sources supply the first and second variable currents.
 12. A semiconductor device comprising: a plurality of data line pairs each comprising a data line and a complementary data line; a plurality of first sensing amplification units corresponding to the plurality of data line pairs, respectively, each first sensing amplification unit comprising a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line of a corresponding one of the plurality of data line pairs; at least one first variable current source supplying or flowing out a first variable current to the first sensing amplifiers; and at least one second variable current source supplying or flowing out a second variable current to the second sensing amplifiers.
 13. The semiconductor device of claim 12, wherein: a current amount of the first variable current is different from a current amount of the second variable current.
 14. The semiconductor device of claim 12, wherein: when a first memory cell connected to the data line is selected, the second variable current is changed to be greater than the first variable current; and when a second memory cell connected to the complementary data line is selected, the second variable current is changed to be less than the first variable current.
 15. The semiconductor device of claim 12, wherein: when the data line pair is precharged with a ground voltage, the first variable current source and the second variable current source supply the first and second variable currents to the first and second sensing amplifiers, respectively; and when the data line pair is precharged with a power supply voltage, the first variable current source and the second variable current source allow the first and second variable currents to flow out of the first and second sensing amplifiers, respectively.
 16. The semiconductor device of claim 12, further comprising: a first memory cell; a second memory cell; a first disconnection unit installed between the first memory cell and the data line, selectively connecting the first memory cell to the data line or disconnecting the first memory cell from the data line; and a second disconnection unit installed between the second memory cell and the complementary data line, selectively connecting the second memory cell to the complementary data line or disconnecting the second memory cell from the complementary data line.
 17. A semiconductor device comprising: a data line pair comprising a data line and a complementary data line; a first sensing amplification unit comprising a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementary data line; a first variable current source supplying or flowing out a first current to the first sensing amplifier; and a second variable current source supplying or flowing out a second current to the second sensing amplifier, wherein when a first memory cell connected to the data line is selected, the second current is supplied or flowed out prior to the first current; and when a second memory cell connected to the complementary data line is selected, the first current is supplied or flowed out prior to the second current.
 18. A method of sensing data stored in a data line pair comprising a data line and a complementary data line by using a first sensing amplifier and a second sensing amplifier, the method comprising: a precharging operation of precharging the data line pair with one of a first voltage level and a second voltage level; and a current controlling operation of supplying or flowing out a first variable current to the first sensing amplifier and supplying or flowing out a second variable current to the second sensing amplifier, wherein a current amount of the first variable current is different from a current amount of the second variable current.
 19. The method of claim 18, wherein: the precharging operation comprises precharging the data line pair with a ground voltage; and the current controlling operation comprises supplying the first and second variable currents to the first and second sensing amplifiers, respectively.
 20. The method of claim 18, wherein: the precharging operation comprises precharging the data line pair with a power supply voltage; and the current controlling operation comprises allowing the first and second variable currents to flow out of the first and second sensing amplifiers, respectively.
 21. The method of claim 18, wherein: when a first memory cell connected to the data line is selected, the second variable current is changed to be greater than the first variable current; and when a second memory cell connected to the complementary data line is selected, the second variable current is changed to be less than the first variable current. 